1. Field of the Invention
The present invention relates generally to structures for spacing a semiconductor device, such as a ball grid array (BGA) package or a flip-chip type semiconductor die, a desired distance from a carrier substrate. The structures of the present invention are also useful for providing stability to the semiconductor device during and following mounting thereof to a carrier substrate. More specifically, the invention pertains to stereolithographically formed spacer structures and to the use of stereolithographic methods to fabricate the spacer structures.
2. State of the Art
Flip-chip technology, including ball grid array packaging technology, is widely used in the electronics industry. In both the generic flip-chip and the ball grid array technologies, a semiconductor device having a pattern of conductive pads on an active surface thereof is joined face down to a higher level substrate, such as a printed circuit board. The contact pads of the higher level substrate are arranged in a mirror image to corresponding contact pads on the semiconductor device. Conductive structures, typically solder bumps (as exemplified by the so-called C-4 technology), conductive epoxy bumps or pillars, conductor-filled epoxy, or an anisotropically z-axis conductive elastomer, are used to join contact pads on the surface of the semiconductor device with their corresponding contact pads on the higher level substrate, establishing electrical communication between the semiconductor device and the higher level substrate.
When the semiconductor device is a flip-chip type semiconductor die, the spacing or pitch between adjacent contact pads, or bond pads, is relatively small. The contact pads themselves are also very small. State of the art flip-chip type semiconductor dice typically include many contact pads in an array on the active surfaces thereof. The high density, small feature size, and large number of conductive pads on state-of-the-art semiconductor dice make the disposal of uniformly sized and configured conductive structures thereon a challenging process. Relatively small variations in the size or shape of the conductive structures can be accommodated for during bonding of the conductive structures to the contact pads of the higher level substrate. However, due to larger dimensional variations in the conductive structures on flip-chip type semiconductor dice, higher bonding temperatures or compressive forces are typically required to ensure the formation of adequate bonds between the bond pads of a flip-chip type semiconductor die and the corresponding contact pads of a higher level substrate. The use of higher temperatures can damage the circuitry and other features of the semiconductor die, as well as impair the integrity of the conductive structures. Overcompression of the conductive structures can also be detrimental. When a compressed conductive structure spreads over and contacts the glass (e.g., borophosphosilicate glass (BPSG), borosilicate glass (BSG), or phosphosilicate glass (PSG)) passivation layer that typically surrounds the bond pads of a semiconductor die, thermal cycling of the semiconductor die during subsequent processing or in use can fracture the conductive structure and diminish the electrical conductivity thereof.
FIG. 4 illustrates overflattened solder bumps 220A. Such overflattening may occur when solder bumps 220 are subjected to overly high temperatures when there are an inadequate number of bumps (see below for further explanation), or when a compressive force 222, 224 is applied to die 200 to ensure the formation of adequate electrical connections between each bond pad 202 of die 200 and its corresponding contact pad 230 of a carrier substrate 210. Where flattened solder bump 220A extends laterally beyond bond pad 202 onto a surrounding glass passivation layer 236, thermal cycling can crack the solder at locations overlying passivation layer 236 and disrupt the electrical continuity between bond pads 202 and their corresponding contact pads 230. It is also desirable to form solder connections with a minimum bump height for enhanced reliability, a relatively taller solder column providing a more reliable connection over time than a squat or flattened bump.
Moreover, some semiconductor dice have bond pads that are positioned in locations that will not adequately and stably support these dice when conductive structures are secured thereto and the dice are disposed face down (i.e., in a flip-chip orientation) over a higher level substrate. Examples of such dice include leads over chip (LOC)-configured semiconductor dice with one or two rows of bond pads along a central axis of the dice and semiconductor dice with bond pads positioned adjacent only a single peripheral edge thereof. Thus, when conductive structures are secured to the bond pads of such a semiconductor die and the semiconductor die is then positioned face down relative to a higher level substrate, the die is prone to being tipped or tilted from an intended orientation that is substantially parallel to a plane of the contact padbearing surface of the higher level substrate. As a consequence, such dice are thought to be unsuitable for flip-chip applications without rerouting of the bond pads to a more stable arrangement. In addition, one or two rows of bond pads bearing solder bumps may not exhibit sufficient surface tension to support the die during reflow of the solder, resulting in collapse or flattening of the molten solder masses and shorting of adjacent connections. Inadequate support strength may also be a problem when other conductive materials are used.
State of the art ball grid array packages, including so-called xe2x80x9cchip-scalexe2x80x9d packages (CSPs), also have numerous densely packed features of small sizes and are, therefore, susceptible to many of the same connection problems described above in reference to other flip-chip type semiconductor dice.
FIG. 1 illustrates an LOC-configured semiconductor die 200 having two centrally located rows of bond pads 202 on an active surface 204 thereof. The two rows of bond pads 202 are located between opposite side edges 206 and 208 of die 200 and extend generally parallel to side edges 226 and 228. Die 200 can be flip-chip connected to a higher level substrate, in this case a carrier substrate 210. Carrier substrate has contact pads 230 exposed at a surface 214 thereof. When die 200 is assembled with carrier substrate 210 in a flip-chip type arrangement, as shown in FIG. 2, die 200 is to be inverted relative to carrier substrate 210, with bond pads 202 being aligned with their corresponding contact pads 230.
Bond pads 202 are typically connected to their corresponding contact pads 230 by way of conductive structures disposed between bond pads 202 and contact pads 230. The conductive structures illustrated in FIGS. 1-7 are solder bumps 220. Typically, solder bumps 220 are first joined to bond pads 202, die 200 is then inverted relative to carrier substrate 210, and finally solder bumps 220 are secured to contact pads 230 by heating the solder to reflow, followed by cooling. As indicated in FIG. 2, the interposition of conductive bumps 220 between bond pads 202 and contact pads 230 ideally causes die 200 to be spaced apart from carrier substrate 210 a certain die-to-substrate distance 218.
As noted previously and illustrated in FIG. 3, since bond pads 202 are arranged on active surface 204 in centrally located rows, die 200 is unstable and may tip or tilt relative to carrier substrate 210. Such tipping or tilting can occur during assembly of die 200 with carrier substrate 210 or during bonding of solder bumps 220 to contact pads 230 if die 200 is not held securely in place by pick and place equipment. Tipping or tilting can also occur after die 200 and carrier substrate 210 have been assembled and solder bumps 220 have been secured between bond pads 202 and contact pads 230 if a greater amount of force 222, 224 is applied to one edge 226, 228 than the amount of force applied to the other edge of die 200.
When tipping or tilting occurs before bond pads 202 and contact pads 230 are joined by solder bumps 220 or other conductive structures, if the angle at which die 200 tips or tilts relative to carrier substrate 210 is great enough, bond pads 202 in one of the rows can be lifted away from contact pads 230 by a sufficient distance to break electrical connections therebetween.
Tilting or tipping of die 200 relative to carrier substrate 210 prior to bonding solder bumps 220 or other conductive structures between bond pads 202 and contact pads 230 can also result in an assembly with conductive structures of different heights and thicknesses. For example, solder bumps 220 can form a variety of nonuniform joints, some of which are shorter and thicker, while others are taller and thinner, than desired. As is well known in the art, thermal stresses or inefficient thermal dissipation can cause failure of solder joints that are too short and thick or too tall and thin or of semiconductor devices joined by such solder joints. A combination of such varied joints experience even greater stresses as die 200 heats and cools during operational cycling.
In addition, if die 200 tips or tilts too much relative to carrier substrate 210 prior to connecting bond pads 202 to contact pads 230, die 200 may contact carrier substrate 210 and thereby cause an electrical short to occur.
If greater forces 222, 224 are applied to one edge 226, 228 of die 200 than to an opposite edge, 226, 228, thereof after bond pads 202 have been connected to their corresponding contact pads 230 by way of conductive structures such as solder bumps 220, one or more of the conductive structures may break, disrupting the electrical connection between one or more of bond pads 202 and their corresponding contact pads 230. In addition, the application of such stresses may cause die 200 itself to tilt or fracture.
FIGS. 5, 6 and 7 illustrate that the same problems can occur with a die 200xe2x80x2 or other semiconductor device having only a single, centrally located row of bond pads 202. While tilting or tipping of die 200xe2x80x2 does not lift a row of solder bumps 220 from contact pads 230 of carrier substrate 210, the other problems discussed above in reference to the tipping or tilting of die 200 or flattening of conductive structures 220 may also occur when die 200xe2x80x2 tips or tilts.
Thus, it is apparent that a need exists for a method and apparatus for adequately spacing a semiconductor device, such as a flip-chip type semiconductor die or a ball grid array package bearing few conductive structures and/or bearing conductive structures in an inherently unstable arrangement, apart from a carrier substrate a distance that facilitates the maintenance of conductive structures in desired shapes and dimensions between the semiconductor device and the carrier substrate. There is also a need for a method and apparatus to stabilize such a semiconductor device on a carrier substrate.
In the past decade, a manufacturing technique termed xe2x80x9cstereolithographyxe2x80x9d, also known as xe2x80x9clayered manufacturingxe2x80x9d, has evolved to a degree where it is employed in many industries.
Essentially, stereolithography, as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or xe2x80x9cslicedxe2x80x9d into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries. This is followed by selective consolidation or fixation of the material to at least a partially consolidated, or semisolid, state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated or fixed or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, surface resolution is highly dependent upon the minimum surface area of the liquid which can be fixed and the minimum thickness of a layer that can be generated. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials, and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques. It has also been recognized in some industries that a stereolithographic object or component may be formed or built around another, pre-existing object or component to create a larger product.
However, to the inventors"" knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other, pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results is required. In particular, the inventor is not aware of the use of stereolithography to fabricate spacer or stabilization structures for use on semiconductor devices, such as flip-chip type semiconductor devices or ball grid array packages. Furthermore, conventional stereolithography apparatus and methods fail to address the difficulties of precisely locating and orienting a number of pre-existing components for stereolithographic application of material thereto without the use of mechanical alignment techniques or to otherwise assuring precise, repeatable placement of components.
The present invention includes spacers, which are also referred to herein as stabilizers, as support structures, or as outriggers, that are positionable on a surface of a semiconductor device, such as on the active surface of a semiconductor die to be flip-chip bonded through use of projecting conductive structures to a higher level substrate, as on the surface of a ball grid array package from which conductive structures protrude. The spacers of the present invention may be used with semiconductor devices having bond pads arranged in such a manner that conductive structures, or elements, secured thereto will not adequately support the semiconductor device when disposed face down on a higher level substrate.
Spacers incorporating teachings of the present invention are configured and located to maintain a substantially parallel relation between a carrier substrate and a semiconductor device to be disposed in a face-down orientation over the carrier substrate. Spacers are also configured to space the semiconductor device and the carrier substrate a minimum distance apart from one another during and after the electrical connection of contact pads of the semiconductor device to corresponding contact pads of the carrier substrate. The spacers are configured to support the semiconductor device in spaced apart relation on the carrier substrate before, during, and after electrical connections are established between the semiconductor device and the carrier substrate.
The spacers of the present invention may be configured as linear structures of substantially uniform height or as columns, bumps, or structures of other shapes that have substantially uniform maximum heights. The height of the spacers on a semiconductor device is preferably less than or equal to the distance a conductive structure, such as a conductive bump, ball, or pillar, will extend between the plane of a surface of the semiconductor device and the plane of the facing surface of the carrier substrate upon which the semiconductor device is to be disposed.
While one or more linearly configured spacers support a semiconductor device disposed upon a carrier substrate by traversing a portion of a surface of the semiconductor device, spacers of other configurations are positioned at locations relative to the surface of the semiconductor device that will provide the desired level of stability. For example, the spacers can be positioned at or near the corners of the surface of the semiconductor device, at or near the edges of the semiconductor device, or in an array over the surface of the semiconductor device.
Preferably, the spacers of the present invention are configured to permit an insulative underfill material to flow into the space between the semiconductor device and the carrier substrate while preventing the occurrence of air pockets or other voids in the underfill material.
The spacers can be fabricated directly on a substrate (e.g., the semiconductor device, a wafer including a plurality of semiconductor devices, or a carrier substrate) or initially fabricated separately from the substrate, then positioned in desired locations on the surface of the substrate and secured thereto. When the spacers of the present invention are fabricated on a semiconductor die, the spacers can be fabricated on a single die, a collection of individual, singulated dice, or on a wafer including a plurality of unsingulated dice. The spacers can similarly be fabricated on other substrates, either singularly or collectively.
The spacers of the invention can be made by various known methods for fabricating features of semiconductor devices. By way of example and not limitation, mask and etch processes can be used to fabricate the spacers from dielectric materials, photoresist material can be patterned to form the spacers, or the spacers can be die cut from a layer of dielectric material. In a preferred embodiment of the invention, stereolithography, or layered manufacturing, processes are employed to fabricate the spacers.
The present invention preferably employs computer-controlled, 3-D CAD initiated, stereolithography techniques to fabricate the spacers of the present invention. When stereolithographic processes are employed, the spacers are each formed as either a single layer or a series of superimposed, contiguous, mutually adhered layers of material.
When the spacers are fabricated directly on a substrate by use of stereolithography, the spacers can be fabricated to extend to a given plane regardless of any irregularities on or nonplanarity of the surface of the semiconductor device on which the spacers are fabricated.
The stereolithographic method of fabricating the spacers of the present invention preferably includes the use of a machine vision system to locate the semiconductor devices on which the spacers are to be fabricated, as well as the features or other components on or associated with the semiconductor devices (e.g., lead frames, bond wires, solder bumps, etc.). A machine vision system is preferably used to direct the alignment of a stereolithography system with the substrate for material disposition purposes. Accordingly, the substrate need not be precisely mechanically aligned with respect to any component of the stereolithography system to practice the stereolithographic embodiment of the method of the present invention.
In a preferred embodiment, the spacers to be fabricated or positioned upon and secured to a substrate, such as a semiconductor die or ball grid array package, in accordance with the invention, are fabricated using precisely focused electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser under control of a computer and responsive to input from a machine vision system, such as a pattern recognition system, to fix or cure selected regions of a layer of a liquid photopolymer material disposed on the substrate.